1. Field of the Invention
The present invention relates to a semiconductor memory device that performs a write operation using a current, and for example, to the arrangement and wiring configuration of write lines in a magnetic random access memory (MRAM).
2. Description of the Related Art
An MRAM (see for example, “IEEE Journal of Solid-State Circuits”, May 2003, Vol. 38, No. 5, pp. 769-773) is a memory that stores data by using the magnetoresistance effect. A voltage is used to write data in conventional flash memory and the like. On the other hand, a current is used to write data in MRAM.
Magnetic tunnel junction (MTJ) elements used in an MRAM utilize the tunneling magnetoresistance effect. An MTJ element generally has an insulating layer and two ferromagnetic layers which sandwich the insulating layer. One of the ferromagnetic layers is called a reference layer and has a direction of magnetization fixed. The other ferromagnetic layer is called a recording layer and does not have a direction of magnetization fixed.
The tunneling magnetoresistance effect is a phenomenon in which a tunneling current varies depending on whether or not the relative relations of the magnetization direction of the two ferromagnetic films are parallel or antiparallel. If the magnetization directions are parallel, the tunneling current is large, so that the MTJ elements have a small resistance. In this case, the resultant data is “0”. On the other hand, if the magnetization directions are antiparallel, the tunnel current is small, so that the MTJ elements have a large resistance. In this case, the resultant data is “1”. A write operation is performed by using a magnetic field induced by a current to set the direction of magnetization of the reference layer to be the same as or opposite to that of the reference layer.
U.S. Pat. No. 6,545,906B1 describes a magnetic memory device employing what is called a toggle write scheme. The magnetic memory device based on this scheme differs from conventional magnetic memory devices in the easy axis of magnetization of the MTJ element, the structure of the MTJ element, and the timing for conducting a write current.
The Jpn. Pat. Appln. KOKAI Publication 2004-220759 and U.S. Pat. No. 6,914,808 describes a magnetic memory device employing what is called a resistance-divided memory cell. In this system, one memory cell has two MTJ elements holding complementary data. A value for a read signal is determined by the ratio of the resistance of one MTJ element to the resistance of the other MTJ element.